1. Field of the Invention
The present invention relates in general to registers in electronic circuits, and, more particularly, to a regenerative latch having a current differential input.
2. Description of the Related Art
Standard sequential logic typically includes a combinational stage driving a voltage signal into a register. For example, one popular implementation of a register having multiplexed inputs includes the use of multiple totem poles of transistors driving a master/slave latch. A two-to-one multiplexer may include two totem poles of four transistors each with the transistors coupled in series between V.sub.DD and ground. Each totem pole has an output in the middle of the totem pole, a select input to the gates of the center transistors and a data input to the gates of the transistors near the reference voltage rails. The master/slave latch is controlled by a clock signal, possibly via transmission gates controlling the flow of the selected data signal from the totem pole mux to RS latches. Alternatively, data signals may be passed through transmission gates controlled by select signals. Other combinational gates such as AND, OR, NOT, NAND and NOR gates drive similar voltage signals into clocked registers.
Because such implementations add to the setup time of the circuit, the transistors of the combinational element are usually made as large as possible with very little fan-out. Very little fan-out requires that the circuit be tapered up or that the output signal be buffered, thereby increasing the amount of layout area used by the circuit. Also, larger transistors increase the area used by repeated circuits. When a circuit is repeated throughout an integrated circuit, such internal increases in required area can significantly impact the total area required. Input capacitance is also higher due to increased width of input transistors.